Transistor having reduced junction leakage and methods of forming thereof

ABSTRACT

A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drain region in the channel layer and a deeply lightly doped drain region at the depth relative to the bottom of the screening layer for reducing junction leakage current. A compensation layer may also be included to prevent loss of back gate control.

RELATED APPLICATION

This application also claims the benefit of U.S. Provisional ApplicationNo. 61/579,142, filed Dec. 22, 2011, the disclosure of which isincorporated by reference herein.

FIELD OF THE INVENTION

Wafers and die manufactured with CMOS compatible die and having highuniformity screen and epitaxial layers are described.

BACKGROUND

Even though electronic devices require matching transistors, in realityit is impossible to manufacture as few as two completely identicaltransistors, especially for nanometer scale transistors. Because ofquantum mechanical effects and the randomness of transistor dopantarrangement, every transistor on a die differs slightly from each other,even if they are spaced only a few nanometers apart. This problem iseven more acute when trying to replicate performance of widely spacedtransistors that may be tens of thousands of nanometers apart on thesame die, transistors on neighboring die in the same wafer, transistorson different wafers, or even transistors manufactured at differentfabricating facilities. Variations can occur due to process differencesresulting in line edge variation, to other unwanted patterning effectsthat change channel, gate, or spacer size, to effective work functionvariation due to composition or crystal formation differences in thegate; or at the atomic scale, to random dopant fluctuations in quantityand spatial positioning of individual dopants in or near the transistorchannel.

Transistor matching issues generally increase in significance astransistors are decreased in size. For typical transistors, transistorwidth and length mismatch typically increases inversely proportionalaccording to the square root of the transistor area. For certaintransistor attributes such as off-state current or threshold voltagevariation, the matching variation in nanometer scale transistors can begreat enough to create an unacceptable die, or result in high devicefailure rates.

BRIEF DESCRIPTION OF THE DRAWINGS

For a complete understanding of the following disclosure, reference isnow made to the following description taken in conjunction with theattached drawings of embodiments, wherein like reference numeralsrepresent like parts, in which:

FIG. 1 illustrates a three dimensional cross section of two adjacenttransistors;

FIG. 2 illustrates an inherent uncertainty in implant placement ofdopant atoms in the respective channels of each transistor;

FIG. 3 illustrates dopant placement along the channel withrepresentative graphs of dopant concentration and placement;

FIG. 4 illustrates a transistor formed on a well incorporating a heavilydoped screening layer that completely extends under a gate area;

FIG. 5 illustrates an epitaxial transistor having a retrograde dopantprofile;

FIG. 6 illustrates a similarly sized transistor with an atomicallyuniform screening layer;

FIG. 7 illustrates etch steps that thin portions of the epitaxial layeror, through well proximity effects, allow an increase or decrease indopant layer concentration near isolation structures;

FIG. 8 illustrates constant thickness epitaxial layers with respect to ascreening layer and a shallow trench isolation (STI) formed post-wellimplant to limit secondary dopant scattering;

FIGS. 9A-9D illustrate an example fabrication process for reducingjunction leakage current in a transistor device;

FIG. 10 illustrates a comparison of a structure without a dLDD region, astructure with a dLDD region having a first dose and a structure with adLDD region 910 having a second dose;

FIG. 11 illustrates the effect on leakage current for various implantconditions of a dLDD region;

FIG. 12 illustrates the effect that a dLDD region has on DIBL and σVt;

FIG. 13 illustrates a phosphorous grading implant for a transistorstructure;

FIG. 14 illustrates a comparison of a structure with different doses ofPhosphorous;

FIG. 15 illustrates a comparison of junction leakage current fordifferent doses of Phosphorous;

FIG. 16 illustrates a comparison of DIBL and σVt at different doses andenergies for Phosphorous;

FIG. 17 illustrates a junction leakage current comparison of the dLDDapproach and the Phosphorous grading approach to a reference that doesnot include these approaches;

FIG. 18 illustrates a comparison of DIBL and σVt for each approach;

FIGS. 19A-19C illustrate the steps for a distributed source/drainimplant process;

FIG. 20 illustrates a reduction in junction abruptness as a result ofdifferent thicknesses for a second offset spacer;

FIG. 21 illustrates a comparison of threshold voltage and junctionleakage for different thicknesses of a second offset spacer anddifferent doses of Phosphorous;

FIG. 22 illustrates a comparison of DIBL and σVt for differentthicknesses of a second offset spacer;

FIG. 23 illustrates a deep implant for a compensation layer to helpcontrol out-diffusion from the source and drain.

DETAILED DESCRIPTION

Digital and analog transistors have been available in decreasing sizesover time, with transistor channel lengths that formerly were tens ofthousands of nanometers being reduced a thousand-fold to a hundrednanometers or less in length. However, because of transistor variationsmaintaining matching electrical characteristics for such downwardlyscaled transistors is difficult at nanometer scales, and can even bemore difficult for supporting circuits requiring highly matchedtransconductance or threshold voltage.

As seen in FIG. 1, illustrating a three dimensional cartoon crosssection of two adjacent transistors, an ideally matched 14 nanometernode CMOS FET transistor pair 100 separated by shallow trench isolation130 includes two channels 110 and 112 formed from a semiconductorcrystalline lattice (typically silicon or silicon-germanium). Thechannels 110 and 112 incorporate a small number of positively ornegatively electrically charged dopant atoms in the lattice such asboron or arsenic. In addition, dopants can include deliberatelyimplanted, but uncharged, diffusion mitigation atoms such as carbon, orvarious contaminant atoms that are either in the crystal lattice or ininter-lattice sites. For a transistor created to have a fourteen (14)nanometer gate length, there might be as few as 200 dopant atoms in achannel. Ideally, each transistor would have identical numbers and typeof dopant atoms in the channel, and placement of the dopant atoms wouldbe the same. However, in practice, as seen in two dimensional cartoonform in FIG. 2, the inherent uncertainty in implant placement of dopantatoms 120 and 122 in the respective channels of each transistor canresult, for example, in distinctly differing chains or clusters ofdopants, or significant gaps in dopant placement, all of which lead tovariations in transistor properties. As will be appreciated, suchfluctuations in dopant number and placement are a major contributor totransistor variation since depth of a depletion zone created by a gateinduced electric field can substantially vary in accordance with dopantdistribution. In addition to electrical effects relating to channelformation, presence of carbon or other uncharged atoms can interferewith charged carrier movement between source and drain of thetransistor, providing variations in carrier mobility andtransconductance.

One way of minimizing such transistor variation and mismatch is togreatly reduce or effectively eliminate dopants in the channel. Forexample, an undoped epitaxial layer capable of acting as a channel canbe selectively grown, with controlled ion implantation to form achannel. Unfortunately, while this can reduce random dopantfluctuations, such substantially undoped channels do not eliminate allproblems associated with dopant variation. Instead, as seen in FIG. 3,which is a cartoon representing dopant placement along the channel, withrepresentative graphs of dopant concentration and placement, variationin placement and amount of dopants around the channel will occur. Suchdopant variations can occur because of out-diffusion from the source ordrain, variations in dopant implant depth along the channel, andvariations in lateral and vertical dopant profiles, all leading tovariations in transistor characteristics. In addition, halo implants areoften used to create a localized, graded dopant distribution near atransistor source and drain that extends into the channel. Halo implantsare often required by transistor designers who want to reduce unwantedsource/drain leakage conduction or “punch through” current. In a mannersimilar to threshold voltage implants, conventional halo implants tendto introduce dopant species into unwanted areas through random dopantfluctuation caused by a variety of factors including scattering effects,crystal lattice channeling effects, lateral straggle, secondarydiffusion, or simple variability in halo dopant energies andimplantation angle.

To provide a range of highly matched transistor device types as seen inFIG. 4, a transistor 200 formed on a well can incorporate a heavilydoped, defined thickness, and highly doped screening layer 212 thatcompletely extends in the lateral direction under a gate area. Inoperation, a gate induced electric field and consequent depletion zoneextends to the screening layer. Preferably, an undoped blanket epitaxiallayer grown on the wafer to form a layer that extends across multipletransistors forms the undoped channel. Alternatively, a selectiveepitaxial channel layer is individually grown on this screening layer.In all instances, efforts are made to maintain the channel layer asundoped, unless the transistor design calls for a slightly dopedchannel, usually in order to achieve a higher threshold voltage.Unwanted diffusion is minimized by use of processing temperatures lowerthan 900 degrees or, or in addition to, Diffusion mitigation carbon capscan be included in the top layers of the screen to avoid the dopantsfrom the screen from diffusing. Halo or threshold implants are minimizedor absent. Since there is minimal dopant presence in the channel, thereis minimal variation in dopant positioning or concentration in thechannel, and transistor channels are well matched. However, this doesnot completely eliminate the problem of transistor mismatch, sinceepitaxial layer thickness can vary under the gate, causing substantialdifferences in threshold voltage or other transistor performancecharacteristics. As seen in FIG. 4, to further reduce transistormismatch, the screening layer 212 is maintained as an atomically uniformlayer that extends a precise distance 216 from a gate dielectric 208.Screen layer 212 extends laterally across the channel to abut the sourceand drain 219, 220. Preferably, the screen layer 212 is positioned to beeither just underneath and abutting the bottom of or is located atapproximately the bottom ⅓ to ¼ of the lightly doped drain extensions221, 222 and extending downward to form a preselected thickness whereinthe screen layer 212 approximately ends a distance above the bottomhorizontal portion of the source and drain 219, 220. The targetedthickness for the screen layer 212 depends on the device design in termsof requirements for threshold voltage and junction leakage, among otherthings, and to what extent a separate anti-punch through region (notshown) is used. The precise depth and thickness of the formed epitaxialchannel layer is maintained over at least 80% of the gate dielectricarea, and depth and thickness may slightly increase or decrease alongthe edge of the gate dielectric due to well proximity or etch effects.Typically, adjacent transistors will have a gate dielectric to screeninglayer thickness that only varies within a one-half nanometer range,while more distant transistors on the same die will still have a channellayer thickness that varies within one nanometer. Additionally, thescreen layer can have a dopant concentration between 1×10¹⁸ and 1×10¹⁹atoms per cubic centimeter or higher concentration, and further has adefined thickness of between five (5) and twenty (20) nanometers thatvaries no more than three (3) nanometers. The highly doped screen layer,together with the anti-punchthrough region (if present), creates astrong body coefficient, making the transistor amenable to beback-biased by electrically connecting a body tap to the screen layer.The back-biasing capability afforded by the highly doped screen layerenables greater flexibility for chip designs. Maintaining a controlledthickness 218 of the screening layer 212 additionally helps to matchleakage current and body bias related performance factors. The tightcontrol of screening layer positioning results in tight control of thedepletion zone when the transistor gate is activated. For comparison, asseen in two dimensional cross section embodied in FIG. 5, a conventionaltransistor 300 having a retrograde dopant profile that is conventionallyformed using buried implants may have an irregular depletion zone 304due to varying concentrations and position of dopants. As seen in FIG.6, similarly sized transistor 302 with an atomically uniform screeninglayer 312 will have a uniform depletion zone 314 set by the screeninglayer 312, and with minimal edge effects.

In certain embodiments, forming a blanket epitaxial layer can furtherinclude steps related to implanting or growing (via incorporation ofdopants or diffusion mitigation atoms such as carbon) various channeldopant profiles deposited on a wafer over the screening layer. Theseprofiles can extend across multiple die and transistor die blocks togive transistors with highly uniform three-dimensional structures. Sucha blanket epitaxial layer, particularly after all well implants aredone, helps to reduce upward migration of dopants emplaced during thewell implants (to form the screening and other doped layers). In otherembodiments, lightly doped Vt adjustment layers can be formed in butafter formation of the epitaxial layer, allowing further adjustment ofvarious transistor characteristics, including threshold voltage andleakage current, particularly in the context of forming a plurality ofdevices having different threshold voltage and other characteristics,for instance to create a SOC.

Transistors that contain the foregoing screening layer transistorstructures are referred to herein as deeply depleted channel fieldeffect transistors (DDC-FETs). DDC-FETs have a number of advantages interms of electrical performance over conventional FETs at the sametechnology node. These advantages include, but are not in any waylimited to, reduced subthreshold conduction (i.e., reduced off-stateleakage current). Because modern integrated circuits typically includemany millions of transistors, reduced off-state leakage current in thesetransistors can provide many benefits including a longer battery-lifefor a mobile device. DDC-FETs are also advantageous in terms of reducedthreshold voltage variation across a given region of an integratedcircuit. This type of threshold voltage variation is referred to assigma Vt (σVt). Circuit designers recognize the many well-known benefitsof reduced variation (or increased uniformity) in the electricalcharacteristics of the devices that are available for them toincorporate into their designs. By way of example and not limitation,the use of devices with a smaller variation in electricalcharacteristics can provide circuit designs with improved performanceand allow the usage of lower supply voltage for the circuits whilemaintaining yield targets. Embodiments of various DDC-FET transistorstructures and manufacturing processes suitable for use in theapplications and processes according to the present disclosure are morecompletely described in U.S. Pat. No. 8,273,617 titled ElectronicDevices and Systems, and Methods for Making and Using the Same, U.S.patent application Ser. No. 12/971,884 titled Low Power SemiconductorTransistor Structure and Method of Fabrication Thereof, U.S. patentapplication Ser. No. 12/971,955 titled Transistor with Threshold VoltageSet Notch and Method of Fabrication Thereof, and U.S. patent applicationSer. No. 12/895,785 titled Advanced Transistors With Threshold VoltageSet Dopant Structures, the disclosures of which are hereby incorporatedby reference in their entirety.

One exemplary process for forming a transistor begins at the wellformation, which may be one of many different processes according todifferent embodiments and examples. Well formation is preferably beforebut may be after STI (shallow trench isolation) formation, depending onthe application and results desired. Boron (B), indium (I) or otheracceptor dopant materials may be used for P-type doping, and arsenic(As), antimony (Sb) or phosphorous (P) and other donor dopant ofmaterials may be used for N-type doping. A germanium (Ge) followed bycarbon (C) implant or in-situ doped carbon epi or cold or roomtemperature carbon implant may optionally be performed to reduce dopantmigration. Well implants may include sequential implant, and/orepitaxial growth and implant of punch through suppression regions, withscreening layers having a defined thickness and higher dopant densitythan the punch through suppression region. Threshold voltage set layerscan be typically formed by implant or diffusion of dopants prior to orinto a previously grown epitaxial layer formed on the already-dopedscreening region.

In some embodiments, the well formation may include a beam line implantof Ge/C followed by or done after B (for N-FET), As (for P-FET), or Sb(for P-FET) in multiple steps so as to form distinct regions for screenand threshold voltage (and anti-punchthrough, if any) followed by anepitaxial (EPI) pre-clean process, and followed finally by non-selectiveblanket EPI deposition. Alternatively, the well may be formed usingplasma implants of the same aforementioned materials, followed by an EPIpre-clean, then finally a non-selective (blanket) EPI deposition. As yetanother alternative, well formation may simply include well implants,followed by in-situ doped EPI (which may be selective or blanket) toform the screening layer and other doped regions. Embodiments describedherein allow for any one of a number of devices configured on a commonsubstrate with different well structures and according to differentparameters. Shallow trench isolation (STI) formation, which, again, mayoccur before or after well formation, may include a low temperaturetrench sacrificial oxide (TSOX) liner at a temperature lower than 900degrees C. A gate stack may be formed or otherwise constructed in anumber of different ways, from different materials, and of differentwork functions. One option is a gate-first process that includesSiON/Metal/Poly and/or SiON/Poly, followed by high-k/Metal Gate. Anotheroption, a gate-last process includes a high-k/metal gate stack whereinthe gate stack can either be formed with “high-k first-Metal gate last”flow or “high-k last-Metal gate last” flow. Yet another option is ametal gate that includes a tunable range of work functions depending onthe device construction. Next, Source/Drain extensions (lightly dopeddrain (LDD)) may be implanted, or optionally may not be implanteddepending on the application. The dimensions of the extensions can bevaried as required, and will depend in part on whether gate spacers areused and requirements for the gate width. In one option, there may be notip (or LDD) implant. Next, the source and drain contacts are formed. Insome embodiments, the PMOS source and drain is created by way ofselective epi. In other embodiments, both PMOS and NMOS source and drainmay be formed by selective epi as performance enhancers for creatingstrained channels and/or reduction of contact resistance.

As illustrated in FIG. 7, in certain embodiments etch steps can thinportions of the epitaxial layer, or preferably, through well proximityeffects, allow an increase or decrease in dopant layer concentrationnear isolation structures. Well proximity effects are described in“Lateral Ion Implant Straggle and Mask Proximity Effect”, IEEETRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 9, SEPTEMBER 2003. Toprevent such implant related effects, use of a screening layer coveredby blanket epitaxial layers can be used, along with post-well implanttrench isolation eliminating much of the dopant scattering attributableto resist or isolation structures. Such structures are illustrated incartoon form as FIG. 8, which shows constant thickness epitaxial layerswith respect to a screening layer, and a shallow trench isolation (STI)formed post-well implant to limit secondary dopant scattering. Suchstructures are described in U.S. patent application Ser. No. 13/469,583titled “Transistor with Reduced Scattered Dopants” the disclosure ofwhich is herein incorporated by reference.

Though shown with a channel layer and screening layer underneath thegate, the transistor structure may be formed as a three layer stack witha screening layer, a threshold voltage control layer, and a channellayer. The threshold voltage control layer may be selectively doped toprovide threshold voltage control for the transistor device.

For operation, the transistor device has a heavily doped screening layerpreferably with a sharp doping profile to provide extremely low DrainInduced Barrier Lowering (DIBL) and threshold voltage variation betweenadjacent transistors (σVt). However, as a general matter, the higherdopant concentration of screen layer 212 with a sharper profile on thebottom can result in a higher junction leakage. This characteristic,while not a problem in most devices including regular or low Vt devices,for those device specifications that require ultra-low leakage current,additional techniques may be desired to help to minimize junctionleakage. Described below are techniques that may be selectively orcomprehensively integrated to achieve lower junction leakage currentwhen called for in the device design. A typical application for thebelow techniques is for High Vt and Ultra-High Vt devices using a highlydoped screening layer.

FIGS. 9A-9D show an example fabrication process for reducing junctionleakage current in the transistor device. In FIG. 9A, the three layerstack is formed underneath a gate 900. The three layer stack includes ascreening layer 902, a threshold voltage control layer 904, and achannel layer 906. Screening layer 902 may have a dopant concentrationbetween 1×10¹⁸ and 1×10²⁰ atoms/cm³ with a thickness preferably between5 and 20 nanometers. Threshold voltage control layer 904 has a dopantconcentration less than screening layer 902, for example between 5×10¹⁷and 1×10¹⁸ atoms/cm³ with a thickness preferably between 5 and 20nanometers. For a NMOS device, screening layer 902 and threshold voltagecontrol layer 904 may be formed with boron or other acceptor dopantmaterials, and may further include a carbon-doped region formed usingin-situ epi or, if implanted, using a cold carbon implant or by firstusing a germanium pre-amorphization implant, in order to form a barrierto inhibit the migration of boron dopant atoms. Channel layer 906 is anundoped epitaxial layer formation with a thickness of 5 to 25nanometers. An optional anti-punchthrough layer 907 may underlie thethree layer stack of screening layer 902, threshold voltage controllayer 904, and undoped channel layer 906.

In FIG. 9B, in an embodiment, a first offset spacer 908 is formed on thevertical sides of gate 900. A deep lightly doped drain (dLDD) region 910is implanted into the structure and targeted to a preselected depth,which may be at a depth of the screening layer 902. The purpose of dLDDregion 910 is to further grade the interface between screening layer 902and the subsequently formed source and drain regions beyond benefitsprovided with a regular LDD. An example condition for forming dLDDregion 910 may include a dose of 5×10¹³ to 1.5×10¹⁴ atoms/cm² at anenergy of 10 to 14 keV. Arsenic may be used as the material for an NMOSdLDD region 910. After formation of dLDD region 910, a shallow lightlydoped drain (sLDD) region 912 is implanted into the structure,preferably using conventional implant methods.

IN FIG. 9C, a second offset spacer 914 is formed preferably on the firstoffset spacer 908. A source region 916 and a drain region 918 arepreferably formed next. FIG. 9D illustrates an exemplary location ofdLDD region 910 in relation to screening layer 902, source region 916,and drain region 918.

FIG. 10 shows a comparison of a structure without a dLDD region 910, astructure with a dLDD region having a dose of 5×10¹³ atoms/cm² and astructure with a dLDD region 910 having a dose of 1×10¹⁴ atoms/cm² in anembodiment. The comparison shows that a reduction in junction abruptnessis achieved through use of dLDD region 910. By reducing the junctionabruptness of screening layer 902 between source region 916 and drainregion 918, a reduction in junction leakage current occurs and thuslowering the band-to-band tunneling rate of the device.

FIG. 11 shows the effect on leakage current for various implantconditions of dLDD region 910 in an embodiment. Generally, increasingthe dose for dLDD region 910 will reduce the junction abruptness at thesource/drain interfaces to screening layer 902. With reduction injunction abruptness afforded by dLDD, junction leakage currents can belowered for devices that include dLDD region 910.

FIG. 12 shows the effect that dLDD region 910 has on DIBL and σVt in anembodiment. DIBL and σVt begin to degrade with increasing doses for dLDDregion 910. However, DIBL and σVt only slightly increase for doses up to1×10¹⁴ atoms/cm². This minimal increase is more than offset by thedecrease in junction leakage current at this dose. As a result, oneexemplary nominal condition for dLDD region 910 for lower junctionleakage current versus short channel control is implanting Arsenic at adose of 1×10¹⁴ atoms/cm² with an energy of 14 keV in an embodiment.

The use of dLDD region 910 provides a direct way to reduce junctionleakage current when implanted directly to the interface of screeninglayer 902 with source region 916 and drain region 918. A ten timesreduction in junction leakage current is achieved using dLDD region 910.The benefits of transistor operation in the embodiment discussed aboveare obtained by only adding a single implant step to the fabricationprocess.

A phosphorous grading technique may be implemented to minimize junctionleakage current by grading the interface between the screening layer andthe source/drain and sLDD regions with a Phosphorous implant. FIG. 13shows an exemplary phosphorous grading implant for the transistorstructure. A grading layer 1301 is implanted at the targeted depth of anNMOS Boron screening layer 1300 prior to source/drain region 1304implant, though the grading layer 1301 can be formed after thesource/drain region 1304 implant is performed. Grading layer may beformed with a high dose of Phosphorous. Instead of implanting Arsenicfor the dLDD region before the implant for the sLDD region, Phosphorousis implanted after formation of a sLDD region 1306 and after the secondspacer which serves as a mask for forming the source/drain. ThePhosphorous implant is physically farther away from screening layer 1302than dLDD region 910 is from screening layer 902 in the dLDD approach.In effect, Phosphorous source/drain grading provides an indirect way toreduce junction leakage current in that it relies on implantedPhosphorous to diffuse towards the inner edges of source/drain region1304 and screening layer 1302 interface.

FIG. 14 shows a comparison of a structure with different doses ofPhosphorous at 2×10¹³ atoms/cm², 7×10¹³ atoms/cm², and 1×10¹⁴ atoms/cm².The comparison shows that a reduction in junction abruptness between thesource/drain and the screening layer is achieved at higher doses ofPhosphorous. In the embodiment, by reducing the junction abruptness ofthe screening layer 1302 between source/drain regions 1304, a reductionin junction leakage current occurs, thus lowering the band-to-bandtunneling rate of the device.

FIG. 15 shows a comparison of junction leakage current for differentdoses of Phosphorous in an embodiment. Increasing the Phosphorous doseleads to a reduction in the junction leakage current. The decrease injunction leakage current is a result of the grading due to the enhancedlateral diffusion of the Phosphorous towards the screening layer 1302and source/drain region 1304 interfaces.

FIG. 16 shows a comparison of DIBL and σVt at different doses andenergies for Phosphorous, in an embodiment. As can be seen in the graph,if the implant energy is too high, a degradation in DIBL and σVt occurs,which can be due to subsurface punchthrough. As seen in the embodiment,an exemplary nominal Phosphorous grading condition for low junctionleakage current and short channel control is approximately a dose of2×10¹⁴ atoms/cm² at an energy of 15 keV.

The use of Phosphorous grading provides an indirect way to reducejunction leakage current when implanted prior to or after thesource/drain region 1304 implant. The benefits of transistor operationdiscussed above are obtained by adding or modifying only a singleimplant step to the fabrication process.

FIG. 17 shows a comparison of junction leakage current reduction for adLDD embodiment, a Phosphorous grading embodiment, and a referenceembodiment that does not include these approaches. As can be seen, aneleven times reduction in junction leakage current can be achieved inthe dLDD approach. A three times reduction in junction leakage currentcan be achieved in the Phosphorous grading approach. In anotherembodiment, the two approaches can be combined to provide furtherreduction in junction leakage current, as much as twenty-eight timescompared to the reference. Thus, an additive effect occurs by performingboth approaches.

FIG. 18 shows a comparison of DIBL and σVt for each embodiment. A slightdegradation in DIBL and σVt occurs when combining the dLDD approach withthe Phosphorous grading approach. However, the reduction in junctionleakage current provided by one or both approaches may more than offsetany increases in DIBL and σVt.

Another technique for reducing junction leakage current is to perform adistributed source/drain implant process. FIGS. 19A-19C show the stepsin an embodiment of this process. In FIG. 19A, after formation of thethree layer stack underneath a gate 1902, a first spacer 1904 is formedon the sidewalls of gate 1902. A sLDD region 1906 is implanted into thestructure. In FIG. 19B, an intermediate spacer 1908 is formed on firstspacer 1904. A dLDD region 1910 is implanted into the structure. In FIG.19C, a second spacer 1912 is formed on intermediate spacer 1908.Alternatively, intermediate spacer 1908 may be etched back beforeforming second spacer 1912. After second spacer 1912 is formed,source/drain regions 1914 are implanted into the structure.

The overall thickness of the spacers in the final device structure maybe set at 25 nanometers. First spacer 1904 may be formed with SiN at athickness of 6 nanometers. Intermediate spacer 1908 may be formed withSiON at a thickness in a range of 0 to 19 nanometers. Second spacer 1912may be formed with SiON to have the total spacer offset be 25nanometers.

The sLDD region 1906 may include a Germanium pre-amorphizing implantfollowed by Carbon implant and Arsenic dopant. The dLDD region 1910 maybe implanted with Phosphorous. The source/drain regions 1914 may beimplanted using Arsenic.

The use of Phosphorous for the material of dLDD region 1910 allows fordLDD region 1910 to be physically closer to the screening layer thanArsenic due to its higher diffusivity. As discussed in the dLDD processand the Phosphorous grading process, the dLDD region 1910 is preferablyimplanted at a depth of the screening layer to influence the screeninglayer to source/drain junction abruptness.

FIG. 20 shows an example of a reduction in junction abruptness as aresult of different thicknesses for intermediate spacer 1908. Junctionleakage current reduces as intermediate spacer 1908 thickness getssmaller.

FIG. 21 shows a comparison of sub-threshold current and junction leakagecurrent for different thicknesses of intermediate spacer 1908 anddifferent doses of Phosphorous. Significant reduction in junctionleakage current can be obtained through modulation of intermediatespacer 1908 thickness and Phosphorous dose. For intermediate spacer 1908thicknesses down to 5 nanometers, there is no significant affect onsub-threshold current.

FIG. 22 shows a comparison of DIBL and σVt for different thicknesses ofintermediate spacer 1908. For thicknesses of intermediate spacer 1908down to 5 nanometers, only minor penalties in DIBL and σVt are seen,insignificant to the overall gain obtained through the reduction ofjunction leakage for the transistor device.

Table I provides a comparison of exemplary conditions in a two offsetspacer implementation versus a three offset spacer implementation. ForSRAM, High Vt and Ultra-High Vt devices, use of an intermediate offsetspacer offers a large advantage in junction leakage current outweighingthe small loss in DIBL and σVt.

TABLE I Two Spacer Usage Three Spacer Usage Intermediate 0 nm (total 7nm to 12 nm Spacer thickness thickness of two (assuming that spacers iswhen added to typically 19 nm) first spacer and third spacer, totalspacer thickness equals 19 nm) Phosphorous Dose 2 × 10¹³ atoms/cm² 7 ×10¹³ atoms/cm² Junction Leakage 284 ρA/μm 25.1 ρA/μm (10× gain) V_(TSAT)202 mV 190 mV V_(TLIN) 240 mV 232 mV DIBL 38 mV 42 mV (11% loss)σV_(TLIN) 3.24 mV 3.38 mV (4.3% loss)

An additional problem arises for narrow-Z as well as short channeldevices during fabrication when back gate control is lost. Silicon lossdue to shallow trench isolation erosion that occurs during a typicalfabrication process allows for the source/drain implants to go deeperthan desired. The source/drain depletion areas may touch each other andbody contact to the anti-punchthrough and/or screening layer isdisconnected. Increasing the dose for an anti-punchthrough layer or thescreening layer may offset this problem but junction leakage current isadversely higher.

FIG. 23 shows an exemplary solution to this problem. At the source/drainmasking step, a deep implant is performed prior to the source/drainregion 2302 implant. A p-type-forming deep implant dopant, such asBoron, is used for a NMOS device. A n-type-forming deep implant dopant,such as Phosphorous or Arsenic, is used for a PMOS device. This implantforms a compensation layer 2304 preferably in alignment with thesource/drain regions, to prevent the source/drain implants fromdiffusing too deep or getting too close to each other. Compensationlayer 2304 can be formed using ion implant using doses that areconsistent with the doses selected for the source/drain implants, andenergies that are either consistent with or slightly higher than theenergies for the source/drain implants. Compensation layer 2304 implantis preferably angled to help ensure placement of compensation 2304 atthe desired location. Other aspects of specific recipes are tailoredusing conventional methods for the given dopant species. Note thatcompensation layer 2304 can be used in the context of a selectiveepitaxially formed source and drain structure as well. Compensationlayer 2304 should have a peak near the bottom of the source/drain regionand form a barrier to prevent the diffusion of the source and drain. Inaddition to preventing the loss of back gate control, this process canbe easily implemented as a single implant step with no additionalmasking step or thermal process required. With the compensation layer2304 being relatively deep, there is no effect on the channel layer.Compensation layer 2304 has a deeper and slower profile having minimalimpact on junction leakage current.

The dLDD technique, the Phosphorous grading technique, the intermediatespacer technique, and the compensation layer technique discussed abovemay be performed alone or in any combination with each other forfabrication of a transistor device.

The foregoing Detailed Description refers to accompanying drawings toillustrate exemplary embodiments consistent with the invention.References in the Detailed Description to “one exemplary embodiment,”“an illustrative embodiment,” “an exemplary embodiment,” and so on,indicate that the exemplary embodiment described may include aparticular feature, structure, or characteristic, but every exemplary orillustrative embodiment may not necessarily include that particularfeature, structure, or characteristic. Moreover, such phrases are notnecessarily referring to the same exemplary embodiment. Further, when aparticular feature, structure, or characteristic is described inconnection with an embodiment, it is within the knowledge of thoseskilled in the relevant art(s) to affect such feature, structure, orcharacteristic in connection with other embodiments whether or notexplicitly described.

The exemplary embodiments described herein are provided for illustrativepurposes, and are not limiting. Other embodiments are possible, andmodifications may be made to the exemplary embodiments within the spiritand scope of the invention. Therefore, the Detailed Description is notmeant to limit the invention. Rather, the scope of the invention isdefined only in accordance with the subjoined claims and theirequivalents.

The foregoing Detailed Description of the exemplary embodiments will sofully reveal the general nature of the invention that others can, byapplying knowledge of those skilled in the relevant art(s), readilymodify and/or adapt for various applications such exemplary embodiments,without undue experimentation, without departing from the spirit andscope of the invention. Therefore, such adaptations and modificationsare intended to be within the meaning and plurality of equivalents ofthe exemplary embodiments based upon the teaching and guidance presentedherein. It is to be understood that the phraseology or terminologyherein is for the purpose of description and not of limitation, suchthat the terminology or phraseology of the present specification is tobe interpreted by those skilled in the relevant art(s) in light of theteachings herein.

What is claimed is:
 1. A method for fabricating a transistor withreduced junction leakage current, comprising: forming a layered stack,the layered stack including at least a doped screening layer and anundoped channel layer over the screening layer; forming a gate stackover the undoped channel layer; forming a first spacer on each sidewallof the gate stack; implanting a shallow lightly doped drain region inthe channel on either side of the gate stack and extending a defineddistance inward from the outer edges of the gate stack; implanting deeplightly doped drain regions on either side of the gate stack tovertically extend the shallow lightly doped drain region a selecteddistance, the deep lightly doped drain region extending no more deeplythan the bottom of the screening layer; forming a second spacer on thefirst spacer; implanting a source region on one side of the gate stackand a drain region on another side of the gate stack.
 2. The method ofclaim 1, wherein the dual lightly doped drain regions are formed withArsenic.
 3. The method of claim 2, wherein the dual lightly doped drainregions are implanted at a dose in a range of 5×10¹³ atoms/cm² to1.5×10¹⁴ atoms/cm² and an energy in a range of 10 to 14 keV.
 4. Themethod of claim 1, further comprising: implanting a grading layer atsubstantially a depth of the screening layer.
 5. The method of claim 4,wherein the grading layer is implanted with Phosphorous.
 6. The methodof claim 5, wherein the Phosphorous is implanted at a dose in a range of7×10¹³ atoms/cm² to 2×10¹⁴ atoms/cm² and an energy in a range of 12 to15 keV.
 7. The method of claim 1, further comprising: forming anintermediate spacer on the first spacer prior to implanting the duallightly doped drain regions.
 8. The method of claim 7, wherein thesecond spacer is formed on the intermediate spacer.
 9. The method ofclaim 7, further comprising: etching back the intermediate spacer. 10.The method of claim 9, wherein the first spacer has a thickness ofapproximately 6 nanometers and the second spacer has a thickness ofapproximately 19 nanometers.
 11. The method of claim 7, wherein thefirst spacer has a thickness of approximately 6 nanometers and theintermediate spacer has a thickness between 0 and 19 nanometers.
 12. Themethod of claim 11, wherein the second spacer has a thickness such thatthe total thickness of the first, intermediate, and second spacers isapproximately 25 nanometers.
 13. The method of claim 1, furthercomprising: implanting a first compensation layer at a depth below thesource region and a second compensation layer at a depth below the drainregion, the first and second compensation layers being substantiallyaligned with the dimensions of the source and drain regions.